Prof. Patrick YUE Received 2024 IEEE Symposium on VLSI Technology and Circuits Test of Time Award
Prof. Patrick YUE from the Department of Electronic and Computer Engineering has been selected to receive the 2024 IEEE Symposium on VLSI Technology and Circuits Test of Time Award for his 1997 paper “On-Chip Spiral Inductors with Patterned Ground Shields for Si-Based RF IC’s”, which is co-authored with his PhD supervisor at Stanford University, Prof. S. Simon WONG.
Established in 2021, the Test of Time Award recognizes the most impactful Symposium papers from each track, published 10 years or more ago, that have established their significance in history.
Prof. Yue worked on the paper while he was a PhD student at Stanford University, supervised by Prof. Wong, who was at that time on his sabbatical leave at HKUST serving as the Acting Head and Professor of the Department of Electrical and Electronic Engineering (now Electronic and Computer Engineering).
The winning paper introduced the first on-chip inductor with a patterned ground shield (PGS) inserted between the spiral inductor and the silicon substrate. PGS’s were realized in standard CMOS technologies using poly-silicon layer without additional processing steps – this was a key factor that drives its adoption and proliferation in low cost RFIC’s. PGS’s increase the inductor quality factor, reduce the substrate noise coupling, and improve the inductor model accuracy by decoupling the lossy silicon substrate. Over the years, PGS’s have become a de facto feature for on-chip inductors and are widely adopted.
Related links:
