Three papers by ECE students showcased again at ISSCC 2016
Three papers by students and professors of ECE were presented at the IEEE International Solid-State Circuits Conference (ISSCC), also known locally as the "Chip Olympiad", that was held on 1-4 February 2016 in San Francisco, USA.
The first paper is entitled "A 4.2ms-Settling-Time 3rd-Order 2.1-GHz Phase-Noise-Rejection PLL Using A Cascaded Time-Amplified Clock-Skew Sub-Sampling DLL" by Zhiqiang Huang and Prof. Howard C. Luong. This paper presents a novel technique to cascade a Type-II PLL with a clock-skew sub-sampling DLL to achieve a record settling time of 4.2ms while significantly improving the performance in terms of the integrated jitter, in-band phase noise, the supply noise rejection, and power consumption.
The second paper is entitled "An 86.0GHz-94.3GHz Transmitter with 15.3-dBm Output Power and 9.6% Efficiency in 65nm CMOS" by Yue Chao and Prof. Howard C. Luong. In this work, a spur-cancellation PLL and a single-stage injection-locked PA are integrated together with power combining and automatic phase-tuning. The 86.0GHz-to-94.3GHz CMOS transmitter prototype measures output power of 15.3dBm and efficiency of 9.3%, which are the best ever reported, with spur suppression improvement of more than 20dB.
The third paper is entitled "A 6.78MHz 6W Wireless Power Receiver with a 3-Level 1X/½X/0X Reconfigurable Resonant Regulating Rectifier" by Lin Cheng, Yat To Wong, Tak Sang Yim, Prof. Wing-Hung Ki and Prof. Chi-Ying Tsui. The reconfigurable receiver realizes one-stage power conversion plus voltage regulation with automatic mode-switching and achieves a maximum rectifier efficiency of 92%.
The IEEE International Solid-State Circuits Conference (ISSCC) is the premier forum for presentation of advances in solid-state circuits and systems-on-a-chip. The conference offers a unique opportunity for engineers working at the cutting edge of IC design and applications to maintain technical currency, and to network with leading experts.
