High Performance Wireline and Optical Communication Transceiver SoC Design
to
10:15 am - 4:10 pm
Leung Yat Sing Lecture Theatre (LT-F), 1/F (near Lift 25, 26), Academic Complex, HKUST
Program Schedule
18th August, 2017
10:15 - 10:30 Registration
10:30 - 10:40 Opening remarks
10:40 - 11:40 Lecture, Prof. Sam Palermo, Texas A&M University
14:30 - 15:30 Lecture, Dr. Hirotaka Tamura, Fujitsu Laboratories,
IEEE Fellow
19th August, 2017
10:30 - 11:30 Lecture, Prof. Jri Lee, National Taiwan University
14:30 - 15:30 Lecture, Prof. C. Patrick Yue, HKUST, IEEE Fellow
15:30 - 16:10 Panel discussion
Advanced Modeling and Design of High-Performance ADC-Based Serial Links
Prof. Sam Palermo, Texas A&M University
Perspectives of the Future of Chip-to-Chip Communications Technology
Dr. Hirotaka Tamura, Fujitsu Laboratories, IEEE Fellow
Advanced Clock and Data Recovery Circuits for High-Speed Wireline Systems
Prof. Jri Lee, National Taiwan University
Recent Developments in Transceiver SoC Design for Next Generation Optical Networks
Prof. C. Patrick Yue, The Hong Kong University of Science and Technology, IEEE Fellow
When
to
Where
Leung Yat Sing Lecture Theatre (LT-F), 1/F (near Lift 25, 26), Academic Complex, HKUST
Language
English
Contact
For inquiry: Please contact Salahuddin RAJU, email rsalahuddin@connect.ust.hk
Registration
https://goo.gl/forms/whS7esOo09FALGGZ2