Examination Committee

Prof Jianzhen YU, CHEM/HKUST (Chairperson)
Prof Amine BERMAK, ECE/HKUST (Thesis Supervisor)
Prof Farid BOUSSAID, School of Electrical, Electronic and Computer Engineering, The University of Western Australia (Thesis Co-supervisor)
Prof Khaled NABIL SALAMA, Computer, Electrical and Mathematical Science and Engineering Division, King Abdullah University of Science and Technology (External Examiner)
Prof Victor SREERAM, School of Electrical, Electronic and Computer Engineering, The University of Western Australia
Prof Kevin CHEN, ECE/HKUST
Prof Volkan KURSUN, ECE/HKUST

Abstract

Sense anything, anywhere, anytime is one of the future goals of semiconductor industry. Combine it with Internet of Things (IoT) and there we go - ubiquitous deployment of smart sensors, preferably operating with passive energy sources like energy harvesting. Minimizing the power consumption of such systems is critical to ensure longer lifetime which leads to lower deployment costs and wide applications spectrum. Arguably, the most power hungry block in the sensing chain is the front-end (instrumentation) amplifier which usually has to meet stringent noise and linearity constraints. This inevitably leads to high power consumption which is usually benchmarked with noise -efficiency factor (NEF).
 
In this work, we present a systematic design methodology which explore the design space (for ultra-low noise instrumentation amplifiers) in all regions of MOSFET operation. Our work is the first of its kind to extend the gm/ID based design methodology for precision instrumentation amplifiers and validate the same through experimental demonstration. Various design trade-offs, including the choice of chopping frequency for minimal residue offset and chopping ripple, gain-precision, bandwidth and area are considered to meet the stringent specifications of a high-performance instrumentation amplifier with minimum power consumption and achieve better than state-of-the-art ‘NEF’.

We also design several readout interfaces for a CMOS-MEMS flow sensing platform. First, an integrated CMOS-MEMS flow sensor is presented which demonstrates a very compact system on chip (SoC) that can sense N2 gas flow ranging from 0 to 26m/s (0-50sccm). Second, we design a nested-chopped CFIA by employing two set of choppers; the outer chopper is clocked at a high frequency to mitigate the flicker noise whereas the inner chopper is clocked at slower frequency to suppress the residue offset. Thus a CFIA with extremely-low offset (400nV) is obtained, which is interfaced with a pulse width modulation (PWM) based ADC to convert the measured flow-rate in digital bits. A fully-differential version of this CFIA, that serves as a front-end IA to a 12-bit incremental ADC is also reported. Third, a multi-path CFIA is presented which employ a nested-chopped low-frequency path (LFP) used to remove the offset and flicker-noise of a high-frequency path (HFP). The function of HFP is to ensure a smooth transfer function for the entire amplifier which had been interrupted with the notches introduced by the ripple-reduction loops.