Examination Committee

Prof Chi Ying TSUI, ECE/HKUST (Chairperson)
Prof Wing Hung KI, ECE/HKUST (Thesis Supervisor)
Prof Philip K T MOK, ECE/HKUST

Abstract

Silicon-based power devices have dominated the market of power switches for the past six decades. Undoubtedly, the trend towards higher efficiency, higher power density and higher switching frequency continues in power electronics applications. Although there have been tremendous improvements on silicon (Si) devices, their performance is inevitably limited by the properties of the Si material, and it is tough to overcome the gap between the performance demanded and the performance delivered. In recent years, researchers have focused on wide-bandgap semiconductor materials such as gallium nitride (GaN). Among various GaN transistors, the enhancement-mode gallium nitride-on-silicon (GaN-on-Si) high electron mobility transistors, commonly known as e-mode GaN HEMTs, have advantages in power electronics applications due to their lower manufacturing cost and outstanding parasitic input/output capacitances. Their higher drain-to-source voltage (VDS) but lower on-resistance (RDS(on)) makes them recognized as one of the most promising candidates to replace Si in the next generation of power switches. However, due to the differences in the electrical ratings of e-mode GaN HEMTs, the driving techniques for Si power transistors cannot be directly applied to drive e-mode GaN HEMTs.

To tackle the above issues, the target of this thesis is to explore the techniques of driving e-mode GaN HEMTs in the MHz-range of switching frequency. First, the characteristics of e-mode GaN devices are briefly introduced and the merits and design challenges of e-mode GaN HEMT driver circuits are discussed. Second, to optimize the power efficiency and reliability of GaN-based power applications, a half-bridge gate driver for e-mode GaN HEMTs with a digital dead-time correction scheme is proposed and implemented using AMS 0.35μm HV CMOS technology. Third, to reduce ringing due to switching, PCB layout optimizations for the half-bridge gate driver are analyzed and incorporated onto the testing board.

To verify the performance of the proposed half-bridge gate driver, an open-loop buck converter is built. Simulation and experiment results show that the converter with digital dead-time correction scheme is able to reduce reverse conduction time to below 1ns. The power efficiency is improved by approximately 4% compared to the fixed dead-time scheme in heavy-load condition. In addition, the layout optimization method reduces the overshoot voltage of the switching node from 100% to below 30%.